1. Field of the Invention
This invention relates to the field of microchip packaging and in particular to routing power and ground connections between the microchip and the package substrate.
2. Discussion of Related Art
Integrated circuits that use high power levels, need a dense pattern of power and ground lines to deliver the required current and achieve expected performance. As the power requirements for a circuit increase, more of the normal interconnect layers (e.g. M5 and M6 on P860) are needed for routing power and ground and they are less available for routing signals. The need for routing power and ground must be addressed by adding more interconnect layers. FIG. 1A is an illustration of a die surface with a C4 bump pattern containing I/O for signal, power, and ground. Challenges to provide finer pitch bumps between a die and a die package have increased routing and routing complexity at the die surface. FIG. 1B is an illustration of a die surface with ABM bumps connected to ground (Vss) and power (Vdd) lines on the chip. With this design, minimum spacing between bumps is approximately 75 microns, bump diameters approximately 75 microns, with a minimum pitch of 150 microns to efficiently route signal lines.
An apparatus, comprising: a die having a surface, comprising: an array of electrically conductive bumps; and a plurality of electrically conductive bars positioned within the array of electrically conductive bumps.